Physical Design Engineer, Forward Deployed Engineering
Senior Physical Design Engineer · Senior · Full Time
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Role
What you'll do.
Join OpenAI's Forward Deployed Engineering team as a Physical Design Engineer, where you'll leverage deep expertise in semiconductor IC physical design to drive production-grade AI system deployments across the chip design lifecycle. This senior technical role combines hands-on physical design authority with customer-facing delivery, where you'll serve as the physical design subject matter expert for semiconductor deployments while partnering with cross-functional teams to translate frontier AI capabilities into tangible improvements to real-world engineering workflows. You'll help scale high-touch customer engagements into repeatable solution patterns while progressively expanding into broader Forward Deployed Engineering responsibilities including customer discovery, solution architecture, and production deployment ownership.
Responsibilities
- Physical Design Subject Matter Expert: Serve as the semiconductor-focused technical authority on the Forward Deployed Engineering team, guiding FDE teams through backend implementation workflows, physical design constraints, and opportunities. Pressure-test AI-assisted solution ideas against real-world physical design realities and ensure customer-facing technical work meets highest quality standards through deep expertise in physical implementation flows.
- AI-Assisted Solution Architecture: Partner with product and engineering teams to shape AI-assisted solutions across the complete physical design workflow including floorplanning, place and route, clock tree synthesis, timing closure, congestion management, power analysis, physical verification, and signoff. Guide feasibility and integration decisions across the entire chip design lifecycle spanning design, verification, and physical design phases.
- Customer Discovery & Technical Advisory: Partner with FDEs during customer discovery and scoping phases to translate ambiguous pain points into clear solution hypotheses, success criteria, and technical plans. Support customer-facing technical conversations as a trusted advisor, engaging credibly with semiconductor leaders to understand their engineering challenges and define success metrics.
- Evaluation Framework Development: Curate evaluation datasets, golden tasks, rubrics, and acceptance criteria for physical design use cases alongside FDEs and customer SMEs. Ensure evaluation workflows reflect real production semiconductor engineering scenarios and meaningful success metrics that validate AI system effectiveness against actual design constraints.
- Prototyping & Validation: Build and guide lightweight prototypes, benchmarks, methodology experiments, and internal tooling that validate market opportunities and accelerate solution development. Create proof-of-concept demonstrations that showcase AI capabilities in physical design workflows while maintaining rigorous engineering standards.
- Technical Education & Team Development: Educate and mentor the broader Forward Deployed Engineering team on physical design concepts, implementation flows, EDA tooling landscape, and critical trade-offs. Build team fluency in backend semiconductor engineering so the organization can engage customers with greater technical depth and confidence across deployments.
- Cross-Functional Collaboration & Roadmap Input: Surface repeated customer signal and emerging patterns to Product and Research teams to inform roadmap prioritization, model behavior optimization, and platform capability development for semiconductor use cases. Work cross-functionally to translate customer feedback into product improvements.
- Forward Deployed Engineering Expansion: Progressively own broader FDE responsibilities including customer discovery leadership, solution architecture, prototype development, production deployment, and technical workstream ownership. Transition from specialized SME support into full Forward Deployed Engineering role with direct customer partnerships and deployment accountability.
Qualifications
What we look for.
Technical
Physical Design Implementation Expertise
Demonstrated mastery in floorplanning, place and route (P&R), clock tree synthesis (CTS), timing closure, power analysis, physical verification, and signoff methodology. Hands-on experience bringing complex ASIC and SoC designs through successful tapeout with deep knowledge of physical implementation trade-offs.
EDA Tool Proficiency
Deep familiarity with industry-standard EDA tool suites including synthesis tools, place and route engines, static timing analysis (STA), physical verification tools, equivalence checking platforms, and power analysis instrumentation. Experience with multiple tool stacks and the ability to work across different semiconductor company environments.
Design Methodology & System Knowledge
Strong understanding of how physical design intersects with microarchitecture, RTL design, verification methodologies, design methodology frameworks, standard cell libraries, process design kits (PDKs), and system-level performance, power, and area (PPA) trade-offs across the semiconductor design stack.
Scripting & Automation
Strong scripting and automation capabilities in Python, Tcl, or equivalent languages. Ability to build tools, workflows, and scripts that optimize physical design processes and integrate with EDA ecosystems.
AI/LLM Application (Preferred)
Exposure to or experience applying artificial intelligence and large language model systems to semiconductor engineering workflows. Understanding of how AI-assisted tools can augment traditional physical design methodologies.
Education
Bachelor's Degree in Electrical Engineering or Computer Engineering
Formal foundation in electrical or computer engineering disciplines with 7+ years of subsequent industry experience in physical design and semiconductor implementation.
Master's Degree in Electrical Engineering or Related Field (Preferred)
Advanced degree in electrical engineering, computer engineering, or related technical field, typically requiring 5+ years of industry experience in IC physical design roles.
Experience
Core Physical Design Experience
7+ years with a Bachelor's degree, 5+ years with a Master's degree, or equivalent industry experience in physical design, physical implementation, or backend signoff for complex ASIC or SoC programs at leading semiconductor companies or design organizations.
Multiple Design Environments
Experience working across multiple semiconductor companies, diverse design environments, or varying tool stacks, bringing perspective shaped by different engineering cultures, methodologies, and organizational approaches to chip design.
Customer-Facing Technical Delivery
Background in solutions engineering, field engineering, customer-facing technical delivery, or consultative technical advisory roles. Demonstrated ability to partner with external customers or strategic accounts in high-trust technical capacity, translating complex engineering challenges into clear business value.
Adjacent Workflow Exposure
Familiarity with adjacent semiconductor design workflows including design methodology, RTL design, and verification processes. Understanding of how physical design decisions cascade through the complete chip design lifecycle.
Skills
Required
Physical Design Expertise
Mastery of place and route, floorplanning, timing closure, clock tree synthesis, power analysis, physical verification, and signoff. Expert-level understanding of physical design trade-offs and constraints.
EDA Tool Proficiency
Deep working knowledge of industry-standard tools including Cadence Innovus/Genus, Synopsys ICC2/Fusion Compiler, timing analysis platforms, physical verification tools, and equivalence checking suites.
Cross-Domain Technical Communication
Ability to translate complex physical design trade-offs clearly in customer-facing, cross-functional, and advisory settings. Proven skill in explaining backend semiconductor engineering to non-specialists while maintaining technical rigor.
Python and Tcl Scripting
Strong proficiency in Python and Tcl scripting languages for automation, tool integration, workflow optimization, and custom methodology development in EDA environments.
Consultative Technical Advisory
Comfort operating as an expert advisor and unblocking teams without being the direct implementation owner. Skill in raising technical quality, shaping decisions, and providing strategic guidance in customer engagements.
Problem Definition & Solution Architecture
Ability to partner during discovery phases to translate ambiguous pain points into clear solution hypotheses, measurable success criteria, and technical implementation plans with realistic feasibility assessments.
Evaluation & Benchmarking Methodology
Experience defining, curating, or scaling evaluation workflows, benchmarks, and acceptance criteria that reflect real-world engineering scenarios and meaningful success metrics.
Preferred
AI/LLM Systems Application
Nice to haveHands-on experience applying artificial intelligence and large language model systems to semiconductor engineering workflows, from ideation through deployment validation.
Multi-Environment Semiconductor Background
Nice to haveDeep experience across multiple semiconductor companies, design environments, or EDA tool ecosystems, bringing diverse perspectives on engineering methodologies and organizational approaches.
Solutions Engineering Experience
Nice to haveTrack record in solutions engineering, field engineering, or customer-facing technical delivery roles where success is measured by customer impact and strategic partnership outcomes.
Design Methodology Expertise
Nice to haveExposure to adjacent semiconductor design workflows including RTL design, design methodology frameworks, and verification approaches, enabling holistic chip design lifecycle perspective.
Forward Deployed Mindset
Nice to haveDemonstrated excitement about growing beyond domain-specific expertise into broader systems-building, customer-facing delivery, and deployment-oriented engineering roles with ownership of technical outcomes.
Tech stack
Languages
Frameworks
Databases
Tools
Other
Compensation
Pay and benefits.
Base·USD 260,000 – 302,000
Equity·Stock options
Full posting
Original listing.
About the Team
OpenAI’s Forward Deployed Engineering team partners with leading semiconductor companies to deploy production-grade AI systems across the entire chip design lifecycle: design, verification, and physical design. We operate at the intersection of customer delivery and core platform development, embedding deeply with customers to translate frontier model capabilities into systems that materially improve engineering workflows and accelerate innovation.
Our work turns early, high-touch deployments into repeatable solution patterns, reference architectures, and evaluation practices that scale across the semiconductor ecosystem.
About the Role
We are seeking a highly skilled Physical Design Engineer to join our semiconductor-focused Forward Deployed Engineering team. This is a senior IC role that will begin with a strong emphasis on physical design expertise, technical judgment, advisory leverage, and customer credibility, with the expectation that the person will grow into a broader Forward Deployed Engineering role over time.
In the near term, you will serve as the team’s physical design SME across semiconductor deployments: helping FDEs, Product, and Research understand backend implementation workflows, pressure-test AI-assisted solution ideas against real physical design constraints, and raise the quality of our customer-facing technical work. You will help the broader team build fluency in implementation flows, EDA tooling, signoff methodology, and the trade-offs that shape physical design decisions in practice.
Over time, we expect this role to expand beyond SME support into broader FDE ownership: partnering directly with customers, shaping deployment strategy, building and iterating production-grade AI systems, driving technical workstreams, and helping turn high-touch semiconductor deployments into repeatable solutions.
This is a strong fit for someone who brings deep physical design expertise today and is excited to grow into a customer-facing, systems-building, delivery-oriented FDE role.
In this role, you will:
Serve as the physical design SME for semiconductor customer engagements, helping FDE teams understand backend implementation workflows, constraints, and opportunities
Partner with FDEs during customer discovery and scoping to translate ambiguous pain points into clear solution hypotheses, success criteria, and technical plans
Support customer-facing technical conversations as a trusted advisor, engaging credibly with technical leaders
Help shape AI-assisted solutions across physical design workflows, including floorplanning, place and route, clocking, timing closure, congestion, power, physical verification, and signoff
Guide feasibility and integration decisions across the entire chip design lifecycle: design, verification, and physical design
Partner with FDEs and customer SMEs to curate evaluation datasets, golden tasks, rubrics, and acceptance criteria for physical design use cases, ensuring evals reflect real workflows and meaningful success metrics
Build or guide lightweight prototypes, benchmarks, methodology experiments, and internal tools that validate opportunities and accelerate solution development
Educate and mentor the broader FDE team on physical design concepts, implementation flows, EDA tooling, and key trade-offs so the org can engage customers with greater depth and confidence
Surface repeated customer signal to Product and Research to help shape roadmap, model behavior, and platform capabilities for semiconductor use cases
Progressively take on broader FDE responsibilities, including customer discovery, solution architecture, prototype development, production deployment, and ownership of technical workstreams
Minimum Qualifications
BS with 7+ years, MS with 5+ years, or equivalent industry experience in physical design, physical implementation, or backend signoff for complex ASIC or SoC programs
Demonstrated success bringing complex designs through tapeout, with hands-on experience in floorplanning, place and route, CTS, timing closure, power analysis, physical verification, and signoff
Deep familiarity with industry-standard EDA tools and flows for synthesis, PNR, STA, physical verification, equivalence checking, and power analysis
Strong understanding of how physical design intersects with microarchitecture, RTL, verification, design methodology, libraries/PDKs, and system-level PPA trade-offs
Strong communication and collaboration skills, with the ability to translate deep technical trade-offs clearly in customer-facing and cross-functional settings
Comfortable operating as a consultative expert and advisor — unblocking teams, shaping decisions, and raising technical quality without necessarily being the direct implementation owner
Strong scripting and automation skills in Python, Tcl, or similar
Excited to grow beyond domain SME responsibilities into a broader Forward Deployed Engineering role, including hands-on solution building, customer-facing delivery, and ownership of deployment outcomes
Preferred Qualifications
Experience working across multiple semiconductor companies, design environments, or tool stacks, with a point of view shaped by different engineering cultures and methodologies
Experience partnering with external customers, strategic accounts, or design partners in a technical advisory capacity
Experience defining or scaling evaluation workflows, benchmarks, or acceptance criteria
Exposure to adjacent workflows such as design and/or verification
Experience applying AI/LLM systems to semiconductor workflows
Prior experience in solutions engineering, field engineering, customer-facing technical delivery, or consultative technical roles
About OpenAI
OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.
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